CY7C63722 Datasheet, PDF (24/58 Pages) Cypress Semiconductor – enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller

FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
Table 13-1. Control Modes to Force D+/D– Outputs
D+/D– Forcing Bit [2:0]
Control Action
Application
000
Not forcing (SIE controls driver)
Any Mode
001
Force K (D+ HIGH, D– LOW)
USB Mode
010
Force J (D+ LOW, D– HIGH)
011
Force SE0 (D– LOW, D+ LOW)
100
Force D– LOW, D+ LOW
PS/2 Mode^[2]
101
Force D– LOW, D+ HiZ
110
Force D– HiZ, D+ LOW
111
Force D– HiZ, D+ HiZ
Note:
2. For PS/2 operation, the D+/D– Forcing Bit [2:0] = 111b mode must be set initially (one time only) before using the other PS/2 force modes.
14.0 USB Device
The CY7C637xx supports one USB Device Address with three endpoints: EP0, EP1, and EP2.
14.1 USB Address Register
The USB Device Address Register contains a 7-bit USB address and one bit to enable USB communication. This register is
cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 14-1 shows the
format of the USB Address Register.
Bit #
7
6
5
4
3
2
1
0
Bit Name
Device
Address
Enable
Device Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 14-1. USB Device Address Register (Address 0x10)
In either USB or PS/2 mode, this register is cleared by both hardware resets and the USB bus reset. See Section 21.3 for more
information on the USB Bus Reset - PS/2 interrupt.
Bit 7: Device Address Enable
This bit must be enabled by firmware before the serial interface engine (SIE) will respond to USB traffic at the address specified
in Bit [6:0].
1 = Enable USB device address.
0 = Disable USB device address.
Bit [6:0]: Device Address Bit [6:0]
These bits must be set by firmware during the USB enumeration process (i.e., SetAddress) to the non-zero address assigned
by the USB host.
14.2 USB Control Endpoint
All USB devices are required to have an endpoint number 0 (EP0) that is used to initialize and control the USB device. EP0
provides access to the device configuration information and allows generic USB status and control accesses. EP0 is bidirectional
as the device can both receive and transmit data. EP0 uses an 8-byte FIFO at SRAM locations 0xF8-0xFF, as shown in Section
8.2.
The EP0 endpoint mode register uses the format shown in Figure 14-2.
Document #: 38-08022 Rev. **
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