CYP15G0401DXA Datasheet, PDF (30/48 Pages) Cypress Semiconductor – Quad HOTLink II Transceiver

PRELIMINARY
IN_SYNC
RXSTx = 101
5
8
4
6
RXSTx = 010
1
RXSTx = 111
RXSTx = 010
6
RESYNC_IN_SYNC
RXSTx=011
CYP15G0401DXA
Reset
NO_SYNC
7
RXSTx = 101
3
4
RESYNC
RXSTx=111
2
2
#
Condition
1 (BOND_INH = LOW OR Master Channel Did Not Bond) AND Deskew Window Expired
2 FRAMCHAR Detected
3 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Any Decoder Error) OR ((BOND_INH = LOW
OR Master Channel Did Not Bond) AND (Deskew Window Expired))
4 Four Consecutive FRAMCHAR Detected
5 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR (Invalid
Minus Valid = 4)
6 Last FRAMCHAR Before a Valid Character AND Bonded to Master Channel
7 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock)
8 Decoder Error
Figure 3. Status Type-B Receive State Machine
Status Type-B Receive State Machine
This machine has four primary states: NO_SYNC, RESYNC,
IN_SYNC, and COULD_NOT_BOND, as shown in Figure 3.
Some of these state can respond with only one status value,
while others can respond with multiple status types.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXSTx[2:0]
bits identify the present state of the BIST compare operation.
The BIST state machine has multiple states, as shown in
Figure 4 and Table 21. When the receive PLL detects an out-
of-lock condition, the BIST state is forced to the Start-of-BIST
state, regardless of the present state of the BIST state ma-
chine. If the number of detected errors ever exceeds the num-
ber of valid matches by greater than 16, the state machine is
forced to the WAIT_FOR_BIST state where it monitors the in-
terface for the first character of the next BIST sequence (D0.0).
Also, if the Elasticity Buffer ever hits and overflow/underflow
condition, the status is forced to the BIST_START until the
buffer is recentered (approximately nine character periods).
To ensure compatibility between the source and destination
BIST operating modes, the sending and receiving ends of the
BIST sequence must both have RXCKSEL = MID or both have
RXCKSEL ≠ MID.
JTAG Support
The CYP15G0401DXA contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, only boundary scan is supported. This capability is
present only on the LVTTL inputs and outputs and the
REFCLK± clock input. The high-speed serial inputs and out-
puts are not part of the JTAG test chain.
Document #: 38-02002 Rev. *B
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