CYP15G0401DXA Datasheet, PDF (13/48 Pages) Cypress Semiconductor – Quad HOTLink II Transceiver

PRELIMINARY
CYP15G0401DXA
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
Bonding Control
BONDST[1:0]
Bidirectional Open
Drain,
internal pull-up
Bonding Status. These signals are only used when multiple devices are bonded togeth-
er. They communicate the status of the present internal bonding and Elasticity Buffer
management events to the slave devices. These outputs change with the same timing
as the receive output data buses, but are connected only to all the slave
CYP15G0401DXA devices.
When MASTER = LOW, these are output signals and present the Elasticity Buffer status
from the selected receive channel of the device configured as the master. Receive
master channel selection is performed using the RXCKB+ and RXCKD+ inputs. These
status outputs indicate one of four possible conditions, on a synchronous basis, to the
slave devices. These condition are:
00—Word Sync Sequence received
01—Add one K28.5 immediately following the next framing character received
10—Delete next framing character received
11—Normal data
These outputs are driven only when the device is configured as a master, all four chan-
nels are bonded together, and the receive parallel interface is clocked by REFCLK↑.
MASTER
LVTTL Input,
static configuration
input
internal pull-down
Master Device Select. When LOW, the present device is configured as the master, and
BONDST[1:0] are outputs. When MASTER = HIGH, BONDST[1:0] are inputs.
MASTER is only interpreted when configured for quad channel bonding, and the receive
parallel interface is clocked by REFCLK↑.
BOND_ALL
Bidirectional Open
Drain,
Internal pull-up
All Channels Bonded Indicator. Active HIGH, wired AND. When HIGH, all receive chan-
nels have detected valid framing.
This output is driven only when all four channels are bonded together, and the receive
parallel interface is clocked by REFCLK↑.
BOND_INH
LVTTL Input,
static configuration
input
Internal pull-up
Parallel Bond Inhibit. Active LOW. When asserted (LOW), this signal inhibits the adjust-
ment of character offsets in all receive channels if the Bonding Sequence has not been
detected in all bonded channels.
When HIGH, all channels that have detected the Bonding Sequence are allowed to align
their Receive Elasticity Buffer pipelines. For any channels to bond, the selected master
channel must be a member of the group.
When multiple devices are used together, the BOND_INH input on all parts must be
configured the same.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high
for ≥5 TCLK cycles, the JTAG test controller is reset.
TCLK
LVTTL Input,
JTAG Test Clock
internal pull-down
TDO
Three-State
LVTTL Output
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
TDI
LVTTL Input,
Test Data In. JTAG data input port.
internal pull-up
Document #: 38-02002 Rev. *B
Page 13 of 48