CY8CLED04_10 Datasheet, PDF (30/37 Pages) Cypress Semiconductor – EZ-Color™ HB LED Controller

CY8CLED04
AC I²C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29. AC Characteristics of the I²C SDA and SCL Pins for Vdd
Symbol
F_SCLI2C
T_HDSTAI2
C
T_LOWI2C
T_HIGHI2C
T_SUSTAI2
C
T_HDDATI2
C
T_SUDATI2
C
T_SUSTOI2
C
T_BUFI2C
T_SPI2C
Description
SCL Clock Frequency
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Pulse Width of spikes are suppressed by the
input filter.
Standard-Mode
Min Max
0
100
4.0
–
4.7
–
4.0
–
4.7
–
0
–
250
–
4.0
–
4.7
–
–
–
Fast-Mode
Min Max
0
400
0.6
–
1.3
–
0.6
–
0.6
–
0
–
100^[16]
–
0.6
–
1.3
–
0
50
Units
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
Notes
Figure 9. Definition for Timing for Fast-/Standard-Mode on the I²C Bus
SDA
T_LOWI2C
T_SUDATI2C
T_HDSTAI2C
T_SPI2C
T_BUFI2C
SCL
S ^THDSTAI2C ^{THDDATI2C T}HIGHI2C
T_SUSTAI2C
Sr
T_SUSTOI2C
P
S
Note
16. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t_SU;DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t_rmax + t_SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-13108 Rev. *C
Page 30 of 37
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