CY8C29466_10 Datasheet, PDF (30/47 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C29466, CY8C29566
CY8C29666, CY8C29866
Table 12-17. AC Chip-Level Specifications (continued)
Symbol
Description
Min
DC_ILO
Internal Low Speed Oscillator Duty Cycle
20
Step24M
24 MHz Trim Step Size
–
Fout48M
48 MHz Output Frequency
46.8
Jitter24M1 24 MHz Period Jitter (IMO)
–
F_MAX
Maximum frequency of signal on row input or row
–
output.
SR_{POWER_UP} Power Supply Slew Rate
–
T_POWERUP Time from end of POR to CPU executing code
–
Typ
Max
Units
Notes
50
80
%
50
48.0
–
49.2^{[9, 11]}
kHz
MHz
Trimmed. Using factory trim
values.
600
–
ps
–
12.3
MHz
–
250
V/ms Vdd slew rate during power up.
16
100
ms Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
PLL
Enable
F_PLL
Figure 12-4. PLL Lock Timing Diagram
T_PLLSLEW
24 MHz
PLL
Gain ⁰
Figure 12-5. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
T_PLLSLEWLOW
24 MHz
F_PLL
PLL
Gain ¹
Figure 12-6. External Crystal Oscillator Startup Timing Diagram
32K
Select
T_OS
32 kHz
F_32K2
Figure 12-7. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F_24M
Figure 12-8. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F _32K2
Document Number: 38-12013 Rev. *M
Page 30 of 47
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