W42C32-05 Datasheet, PDF (3/8 Pages) Cypress Semiconductor – Spread Spectrum Frequency Timing Generator

W42C32-05
Functional Description
The W42C32-05 uses a phase-locked loop (PLL) to multiply
the frequency of a low-cost, low-frequency crystal up to the
desired clock frequency. The basic circuit topology is shown in
Figure 1. An on-chip crystal driver causes the crystal to oscil-
late at its fundamental. The resulting reference signal is divid-
ed by Q and fed to the phase detector. The VCO output is
divided by P and also fed back to the phase detector. The PLL
will force the frequency of the VCO output signal to change
until the divided output signal and the divided reference signal
match at the phase detector input. The output frequency is
then equal to the ratio of P/Q times the reference frequency.
The unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum frequency timing generation, EMI reduc-
tion depends on the shape, modulation percentage, and fre-
quency of the modulating waveform. While the shape and fre-
quency of the modulating waveform in the W42C32 are fixed,
the modulation percentage may be varied.
Using frequency select bits (FS2:0 pins), various spreading
percentages for different input frequency ranges can be cho-
sen. For example, refer to the W42C32-05 in Table 1. If the
logic level on FS2:0 = 000, then an input reference frequency
between 14 and 24 MHz will produce an output frequency at
twice the reference frequency with a spread of ±2.5%.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between ±0.875% and ±2.5% are
most common.
Additional Features of the W42C32-05
A RESET pin is available to aid in applications which have
multiple PLL clock generators. When a reset is issued, the
modulation profile shown in Figure 3 is reset to its starting
point. This feature is necessary for applications in which two
spread spectrum systems must synchronize with each other.
The REFOUT out pin provides a buffered version of the input
clock frequency.
The SSON# pin disables the spread spectrum function when
set to logic HIGH. Otherwise, an internal pull-down resistor
leaves this feature enabled.
The PD# pin reduces power consumption and disables the
clock outputs when set to logic LOW. Otherwise, an internal
pull-up resistor places the W42C32-05 into normal mode.
V_DD
X1
XTAL
Freq.
X2
Divider
Q
Phase
Detector
Charge
Pump
Σ
VCO
Post
Dividers
Crystal load
capacitors
as needed
Feedback
Divider
P
Modulating
Waveform
PLL
GND
Figure 1. System Block Diagram (Concept, not actual implementation)
CLKOUT
3