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W42C32-05 Datasheet, PDF (2/8 Pages) Cypress Semiconductor – Spread Spectrum Frequency Timing Generator
W42C32-05
Pin Definitions[1]
Pin Name Pin No.
Pin
Type
Pin Description
CLKOUT
8
O
Output Modulated Frequency: Frequency is set using FS0:2 (refer to Table 1).
REFOUT
16
O
Reference Output: A buffered version of the input frequency.
X1
2
I
Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as either an external crystal connection, or as an external reference
frequency input.
X2
3
I
Crystal Connection: If using an external reference, this pin must be left unconnected.
SSON#
13
I
Spread Spectrum Control (active LOW): Pulling this input signal HIGH turns the internal
modulating waveform off. This pin has an internal pull-down resistor.
FS0
6
I
Frequency Selection Bit 0: This pin selects the frequency and spreading characteristics.
Refer to Table 1. This pin has an internal pull-up resistor.
FS1
14
I
Frequency Selection Bit 1: This pin selects the frequency and spreading characteristics.
Refer to Table 1. This pin has an internal pull-up resistor.
FS2
15
I
Frequency Selection Bit 2: This pin selects the frequency and spreading characteristics.
Refer to Table 1 (note the VDD specification). This pin has an internal pull-up resistor.
PD#
1
I
Power-down (active LOW): Enabling power-down reduces current consumption and
disables the clock outputs. This pin has an internal pull-up resistor.
REFEN#
9
I
Reference Clock Selection Input: Pulling this signal LOW turns the REFOUT clock
output on. This pin has an internal pull-up resistor.
RESET
12
I
Reset: A reset starts the spread spectrum modulating frequency at the beginning point
of the modulation profile. This pin has an internal pull-down resistor. To reset the spread
spectrum modulating frequency, pull this pin from LOW to HIGH.
VDD
11
P
Power Connection: Connected to either 3.3V or 5.0V power supply. VDD and AVDD must
be the same voltage level.
AVDD
GND
10
P
Analog Power Connection: Connected to either 3.3V or 5.0V power supply. VDD and
AVDD must be the same voltage level.
4
G
Ground Connection: Connect to the common system ground plane.
AGND
5
G
Analog Ground Connection: Connect to the common system ground plane.
TEST
7
I
Three-state Input: Pulling this input pin and REFEN# pin HIGH, CLKOUT will be
three-stated. This pin has an internal pull-down resistor.[2]
Notes:
1. Pull-up resistors not CMOS level.
2. Pulling PD# and REFEN# input pins HIGH, REFOUT will be three-stated.
2