W320-04 Datasheet, PDF (3/17 Pages) SpectraLinear Inc – 200 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

W320-04
Function Table^[1]
S2 S1 S0
CPU
(MHz)
66BUFF[0:2]/
3V66[0:1] 3V66[2:4] 66IN/3V66_5 PCI_F/PCI
(MHz)
(MHz)
(MHz)
(MHz)
1 0 0 66 MHz 66 MHz 66IN
66 MHz Input 66IN/2
1 0 1 100 MHz 66 MHz 66IN
66 MHz Input 66IN/2
1 1 0 200 MHz 66 MHz 66IN
66 MHz Input 66IN/2
1 1 1 133 MHz 66 MHz 66IN
66 MHz Input 66IN/2
0 0 0 66 MHz 66 MHz 66 MHz
66 MHz
33 MHz
0 0 1 100 MHz 66 MHz 66 MHz
66 MHz
33 MHz
0 1 0 200 MHz 66 MHz 66 MHz
66 MHz
33 MHz
0 1 1 133 MHz 66 MHz 66 MHz
66 MHz
33 MHz
Mid 0 0 Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Mid 0 1 TCLK/2 TCLK/4 TCLK/4
TCLK/4
TCLK/8
Mid 1 0 Reserved Reserved Reserved
Reserved
Reserved
Mid 1 1 Reserved Reserved Reserved
Reserved
Reserved
REF0(MHz)
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
TCLK
Reserved
Reserved
USB/DOT
(MHz)
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Hi-Z
TCLK/2
Reserved
Reserved
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
5, 6, 7
–
–
Swing Select Functions
Mult0
0
1
Board Target Trace/Term Z
50Ω
50Ω
Reference R, IREF ₌ V_DD/(3*Rr)
Rr = 221 1%, IREF = 5.00 mA
Rr = 475 1%, IREF = 2.32 mA
Output Current V_OH @ Z
I_OH = 4*IREF 1.0V @ 50
I_OH = 6*IREF 0.7V @ 50
Clock Driver Impedances
Buffer Name
CPU, CPU#
REF
PCI, 3V66, 66BUFF
USB
DOT
V_DD Range
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
Buffer Type
Type X1
Type 5
Type 5
Type 3A
Type 3B
Min. Ω
12
12
12
12
Impedance
Typ. Ω
50
30
30
30
30
Max. Ω
55
55
60
60
Clock Enable Configuration
VCOS/
PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT OSC
0
X
X
IREF*2 FLOAT LOW LOW LOW LOW LOW
OFF
1
0
0
ON FLOAT ON
ON
ON OFF
ON
ON
1
0
1
ON LOW ON
ON
ON ON
ON
ON
1
1
0
ON
ON ON
ON
ON OFF
ON
ON
1
1
1
ON
ON ON
ON
ON ON
ON
ON
Note:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation
3. Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
6. Required for DC output impedance verification.
7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
Document #: 38-07010 Rev. *C
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