W305B Datasheet, PDF (3/21 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic

W305B
W305B
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 kΩ
Output Strapping Resistor
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W305B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel^® archi-
tecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Upon power-up the power on strap option pins act as a logic
input. An external 10-kΩ strapping resistor should be used.
Figure 1 shows a suggested method for strapping resistor
connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below
target but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.
Offsets Among Clock Signal Groups
Figure 2, Figure 3, and Figure 4 represent the phase
relationship among the different groups of clock outputs from
W305B under different frequency modes.
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 16.6-MHz
CPU 66 Period
Hub-PCI
SDRAM 100 Period
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
Document #: 38-07262 Rev. *B
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