W254B Datasheet, PDF (3/17 Pages) SpectraLinear Inc – 133MHz Spread Spectrum FTG for Mobile Pentium® III Platforms

W254B
W254B
Power-on
Reset
Timer
V_DD
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 kΩ
(Load Option 1)
10 kΩ
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W254B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics-integrated core logic.
Functional Description
I/O Pin Operation
Pins 6 and 7 are dual-purpose l/O pins. Upon power-up these
pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins then become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
each l/O pin and ground or VDDQ3. Connection to ground
sets a latch to “0”, connection to VDDQ3 sets a latch to “1”.
Figure 1 shows one suggested method for strapping resistor
connection.
Upon W254B power-up, the first 2 ms of operation is used for
input logic selection. During this period, the PCI_F and PCI1
clock output buffers are three-stated, allowing the output
strapping resistor on each l/O pin to pull the pin and its asso-
ciated capacitive clock load to either a logic HIGH or logic
LOW state. At the end of the 2-ms period, the established
logic 0 or 1 condition of each l/O is pin is latched. Next the
output buffers are enabled, converting all l/O pins into operat-
ing clock outputs. The 2-ms timer starts when VDDQ3
reaches 2.0V. The input bits can only be reset by turning
VDDQ3 off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock output is 40Ω (nominal), which is minimally
affected by the 10-kΩ strap to ground or VDDQ3. As with the
series termination resistor, the output strapping resistor
should be placed as close to the l/O pin as possible in order
to keep the interconnecting trace short. The trace from the
resistor to ground or VDDQ3 should be kept less than two
inches in length to prevent system noise coupling during
input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered, assum-
ing that VDDQ3 has stabilized. If VDDQ3 has not yet reached
full value, output frequency initially may be below target but
will increase to target once VDDQ3 voltage has stabilized. In
either case, a short output clock cycle may be produced from
the CPU clock outputs when the outputs are enabled.
CPU/ SDRAM Frequency Selection
CPU output frequency is selected with I/O pins 6 and 7. For
CPU/SDRAM frequency programming information refer to
Table 2. Alternatively, frequency selections are available
through the serial data interface.
Table 2. Frequency Select Truth Table^[2]
Input Address
FS1
FS0
CPU
SDRAM
Output Frequencies
48 MHz^[3]
PCI
APIC
0
0
66
100
0
1
100
100
48 MHz
1
0
133
133
33 MHz
1
1
133
100
Notes:
2. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
3. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
REF
3V66
14.318 MHz
66 MHz
Document #: 38-07233 Rev. *A
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