W254B Datasheet, PDF (1/17 Pages) SpectraLinear Inc – 133MHz Spread Spectrum FTG for Mobile Pentium® III Platforms

W254B
133-MHz Spread Spectrum FTG for
Mobile Pentium® III Platforms
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology (–0.5% and ±0.5%)
• Single chip system FTG for Mobile Intel^® Platforms
• Two CPU outputs
• Seven copies of PCI clock (one Free Running)
• Seven SDRAM clock (one DCLK for Memory Hub)
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video DOT clock
• Three 3V66 Hublink/AGP outputs
• One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)
• One APIC outputs
• One buffered reference output
• Supports frequencies up to 133 MHz
• SMBus interface for programming
• Power management control inputs
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
CPU Output Skew: ......................................................150 ps
3V66 Output Skew: .....................................................175 ps
APIC, SDRAM Output Skew: ......................................250 ps
PCI Output Skew:........................................................500 ps
VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM): ......... 3.3V±5%
VDDQ2 (CPU, APIC):....... 2.5V±5%in Selectable Frequency
Table 1. Pin Selectable Frequency
Input
Address
Output Frequencies
FS1 FS0 CPU SDRAM 48MHz PCI APIC REF 3V66
0 0 66 100
0 1 100 100
48
1 0 133 133 ^MHz
33 14.318 66
MHz MHz MHz
Key Specifications
1 1 133 100
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
Block Diagram
Pin Configuration
X1
XTAL
PLL Ref Freq
X2
OSC
PLL 1
Divider
Network
Stop
Clock
Control
CPU_STP#
PWR_DWN#
PCI_STP#
Stop
Clock
Control
PLL2
SDATA
SCLK
SMBus
Logic
VDD_REF
REF
VDD_CPU
CPU
CPU_F
VDD_APIC
APIC
VDD_SDRAM
DCLK
SDRAM0:5
VDD_PCI
PCI_F/FS0
PCI1/FS1
PCI2:6
VDD_3V66
3V66_0:1
3V66_AGP
VDD_48
USB (48MHz)
DOT (48MHz)
VCH_CLK
Intel and Pentium are registered trademarks of Intel Corporation.
VDD_REF 1
X1 2
X2 3
GND_REF 4
GND_PCI 5
PCI_F/FS0^ 6
PCI1/FS1^ 7
PCI2 8
VDD_PCI 9
PCI3 10
PCI4 11
PCI5 12
PCI6 13
VDD_3V66 14
3V66_0 15
3V66_1 16
3V66_AGP 17
GND_3V66 18
VCH_CLK 19
GND_48 20
USB 21
DOT 22
VDD_48 23
GND_CORE 24
48 REF
47 APIC
46 VDD_APIC
45 VDD_CPU
44 CPU
43 CPU_F
42 GND_CPU
41 _{GND_SDRAM}
40 _SDRAM0
39 _SDRAM1
38 VDD_SDRAM
37 SDRAM2
36 SDRAM3
35 GND_SDRAM
34 SDRAM4
33 _SDRAM5
32 _DCLK
31 _{VDD_SDRAM}
30 CPU_STP#
29 _{PCI_STP#}
28 _{PWR_DWN#}
27 _SCLK
26 _SDATA
25 VDD_CORE
Note:
1. Internal pull-down or pull-up resistors present on inputs
marked with * or ^ respectively. Design should not rely solely
on internal pull-up or pull-down resistor to set I/O pins HIGH
or LOW respectively.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07233 Rev. *A
Revised December 22, 2002