W216 Datasheet, PDF (3/14 Pages) Cypress Semiconductor – Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

PRELIMINARY
W216
Pin Definitions (continued)
Pin Name
Pin No.
Pin
Type
Pin Description
GND
4, 10, 23, 26, G Ground Connections: Connect all ground pins to the common system ground plane.
34, 42, 48, 53
Overview
The W216 was designed as a single-chip alternative to the
standard two-chip Intel 440BX AGPset clock solution. It pro-
vides sufficient outputs to support most single-processor, four
SDRAM DIMM designs.
Functional Description
I/O Pin Operation
Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon power-
up these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V_DD. Connection to ground sets a
latch to “0,” connection to V_DD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W216 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the five I/O pins (2, 8,
9, 29, 30) are three-stated, allowing the output strapping resis-
tor on the l/O pins to pull the pins and their associated capac-
itive clock load to either a logic HIGH or LOW state. At the end
of the 2-ms period, the established logic “0” or “1” condition of
the l/O pin is latched. Next the output buffer is enabled, con-
verting the l/O pins into operating clock outputs. The 2-ms tim-
er starts when V_DD reaches 2.0V. The input bits can only be
reset by turning V_DD off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock output (<40Ω, nominal), which is minimally af-
fected by the 10-kΩ strap to ground or V_DD. As with the series
termination resistor, the output strapping resistor should be
placed as close to the l/O pin as possible in order to keep the
interconnecting trace short. The trace from the resistor to
ground or V_DD should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V_DD has stabilized. If V_DD has not yet reached
full value, output frequency initially may be below target but will
increase to target once V_DD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
V_DD
Output Strapping Resistor
W216
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 kΩ
(Load Option 1)
10 kΩ
(Load Option 0)
Series Termination Resistor
R
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
W216
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 kΩ
V_DD
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
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