CYV15G0104 Datasheet, PDF (3/28 Pages) Cypress Semiconductor – Independent Clock HOTLink II Serializer and Reclocking Deserializer

PRELIMINARY
CYV15G0104TRB
Reclocking Deserializer Path Block Diagram
TRGRATEA
TRGCLKA
x2
SDASEL[2..1]A[1:0]
LDTDEN
INSELA
INA1+
INA1–
INA2+
INA2–
ULCA
SPDSELA
RXPLLPDA
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Recovered Character Clock
10
RXBISTA[1:0]
RXRATEA
Recovered Serial Data
JTAG
Boundary
Scan
Controller
10
10
÷2
RESET
TRST
TMS
TCLK
TDI
TDO
LFIA
RXDA[9:0]
BISTSTA
RXCLKA+
RXCLKA–
ROE[2..1]A
Reclocker
Output PLL
Clock Multiplier
ROE[2..1]A
RECLKOA
REPDOA
Character-Rate Clock
Bit-Rate Clock
Serializer Path Block Diagram
REFCLKB+
REFCLKB–
TXRATEB
SPDSELB
TXCLKOB
TXERRB
TXCLKB
TXCKSELB
01
Bit-Rate Clock
Transmit PLL
Transmit PLL
Cl_Co_loc_ck_k M_Muu_ltl_it_pip_lieli_rer
TOE[2..1]B
Character-Rate Clock
PABRSTB
TXBISTB
TXDB[9:0]
10
10
10
10
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
= Internal Signal
TOE[2..1]B
TOUTB1+
TOUTB1–
TOUTB2+
TOUTB2–
Document #: 38-02100 Rev. **
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