CYV15G0104 Datasheet, PDF (10/28 Pages) Cypress Semiconductor – Independent Clock HOTLink II Serializer and Reclocking Deserializer

PRELIMINARY
CYV15G0104TRB
Pin Definitions (continued)
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer
Name
ROE2A
ROE1A
PABRSTB
I/O Characteristics
Internal Latch^[6]
Internal Latch^[6]
Internal Latch^[6]
Signal Description
Reclocker Differential Serial Output Driver 2 Enable.
Reclocker Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Analog I/O
TOUTB1±
CML Differential
Output
Transmitter Primary Differential Serial Data Output. The transmitter TOUTB1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-
coupled for PECL-compatible connections.
TOUTB2±
CML Differential
Output
Transmitter Secondary Differential Serial Data Output. The transmitter TOUTB2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled
for PECL-compatible connections.
ROUTA1±
CML Differential
Output
Reclocker Primary Differential Serial Data Output. The reclocker ROUTA1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-
coupled for PECL-compatible connections.
ROUTA2±
CML Differential
Output
Reclocker Secondary Differential Serial Data Output. The reclocker ROUTA2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled
for PECL-compatible connections.
INA1±
Differential Input
Primary Differential Serial Data Input. The INA1± input accepts the serial data
stream for deserialization. The INA1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELA = HIGH.
INA2±
Differential Input
Secondary Differential Serial Data Input. The INA2± input accepts the serial data
stream for deserialization. The INA2± serial stream is passed to the receiver CDR
circuit to extract the data content when INSELA = LOW.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained
high for ≥5 TCLK cycles, the JTAG test controller is reset.
TCLK
LVTTL Input,
internal pull-down
JTAG Test Clock.
TDO
3-State LVTTL
Output
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
TDI
LVTTL Input,
Test Data In. JTAG data input port.
internal pull-up
TRST
LVTTL Input,
internal pull-up
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
V_CC
GND
+3.3V Power.
Signal and Power Ground for all internal circuits.
CYV15G0104TRB HOTLink II Operation
The CYV15G0104TRB is a highly configurable, independent
clocking device designed to support reliable transfer of large
quantities of digital video data, using high-speed serial links
from multiple sources to multiple destinations.
Document #: 38-02100 Rev. **
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