CY7C1516AV18 Datasheet, PDF (3/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 2-Word Burst Architecture

PRELIMINARY
Logic Block Diagram (CY7C1518AV18)
CY7C1516AV18
CY7C1527AV18
CY7C1518AV18
CY7C1520AV18
Burst
A0
Logic
22 ²¹
A_{(21: 0)}
A_(21:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
V_REF
R/W
BWS_{[1: 0]}
Control
Logic
Write
Reg
Write
Reg
4M x 18 Array
Read Data Reg.
36 ₁₈
18
Output
R/W
Logic
Control
C
C
Reg.
Reg.
Reg.
18
18
18
CQ
CQ
DQ_{[17: 0]}
Logic Block Diagram (CY7C1520AV18)
Burst
A0
Logic
21 ²⁰
A_(20:0)
A_(20:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
Write
Reg
Write
Reg
2M x 36 Array
Read Data Reg.
V_REF
R/W
BWS_[3:0]
Control
Logic
72 ₃₆
36
36
Output
R/W
Logic
Control
C
C
Reg.
Reg. ³⁶
Reg.
36
36
CQ
CQ
DQ_{[35: 0]}
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
300 MHz
300
900
278 MHz
278
860
250 MHz
250
800
200 MHz
200
700
167 MHz
167
650
Unit
MHz
mA
Document #: 001-06982 Rev. *B
Page 3 of 28
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