CY7C1510JV18_09 Datasheet, PDF (3/26 Pages) Cypress Semiconductor – 72-Mbit QDR™-II SRAM 2-Word Burst Architecture

Logic Block Diagram (CY7C1512JV18)
CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18
D_[17:0]
18
A_(20:0) ²¹
Address
Register
K
K
DOFF
V_REF
WPS
BWS_[1:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
21
A_(20:0)
Read Data Reg.
36
18
18
Control
Logic
RPS
C
C
Reg.
Reg. ¹⁸
Reg.
18
18
CQ
CQ
Q_[17:0]
Logic Block Diagram (CY7C1514JV18)
D_[35:0]
36
A_(19:0) ²⁰
Address
Register
K
K
DOFF
V_REF
WPS
BWS_[3:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
20
A_(19:0)
Read Data Reg.
72
36
36
Control
Logic
RPS
C
C
Reg.
Reg. ³⁶
Reg.
36
36
CQ
CQ
Q_[35:0]
Document #: 001-14435 Rev. *F
Page 3 of 26
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