CY7C09269A Datasheet, PDF (3/17 Pages) Cypress Semiconductor – 16K x16/18 Synchronous Dual Port Static RAM

Pin Configurations (continued)
100-Pin TQFP (Top View)
CY7C09269A
CY7C09369A
A9L
A10L
A11L
A12L
A13L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VCC
FT/PIPEL
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
CY7C09369A (16K x 18)
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R
A9R
A10R
A11R
A12R
A13R
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
Selection Guide
f_MAX2 (MHz) (Pipelined)
Max Access Time (ns)
(Clock to Data, Pipelined)
Typical Operating Current I_CC (mA)
Typical Standby Current for I_SB1 (mA)
(Both Ports TTL Level)
Typical Standby Current for I_SB3 (mA)
(Both Ports CMOS Level)
CY7C09269A
CY7C09369A
-6^[1]
100
6.5
250
45
0.05
CY7C09269A
CY7C09369A
-7
83
7.5
235
40
0.05
CY7C09269A
CY7C09369A
-9
67
9
215
35
0.05
CY7C09269A
CY7C09369A
-12
50
12
195
30
0.05
Document #: 38-06050 Rev. *A
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