CY7C09269A Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 16K x16/18 Synchronous Dual Port Static RAM

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CY7C09269A
CY7C09369A
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269A/369A)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 100-
MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5^[1]/7.5/9/12 ns (max.)
Logic Block Diagram
R/W_L
UB_L
16K x16/18 Synchronous
Dual Port Static RAM
• Low operating power
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial temperature range
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT709269
R/W_R
UB_R
CE_0L
1
CE_1L
0
LB_L
0/1
OE_L
1
CE_0R
0
CE_1R
0/1
LB_R
OE_R
FT/Pipe_L
[2]
I/O_8/9L–I/O_15/17L
1b 0b 1a 0a
0/1 b
a
8/9
[3]
I/O_0L–I/O_7/8L
A_0L–A_13L
CLK_L
ADS_L
CNTEN_L
CNTRST_L
8/9
14
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
Notes:
1. See page 6 for Load Conditions.
2. I/O₈–I/O₁₅ for x16 devices; I/O₉–I/O₁₇ for x18 devices.
3. I/O₀–I/O₇ for x16 devices. I/O₀–I/O₈ for x18 devices.
0a 1a 0b 1b
a
b 0/1
8/9
FT/Pipe_R
[2]
I/O_8/9R–I/O_15/17R
8/9
14
Counter/
Address
Register
Decode
[3]
I/O_0R–I/O_7/8R
A_0R–A_13R
CLK_R
ADS_R
CNTEN_R
CNTRST_R
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06050 Rev. *A
Revised December 27, 2002