CY2SSTV850 Datasheet, PDF (3/11 Pages) Cypress Semiconductor – Differential Clock Buffer/Driver

CY2SSTV850
Function Table
AVDD
GND
GND
2.5V
2.5V
2.5V
Inputs
CLKINT
CLKINC
L
H
H
L
L
H
H
L
Nom Design Nom Design
<20 MHz <30 MHZ <20 MHz <30 MHz
YT(0:9)^[3]
L
H
L
H
Hi-Z
Outputs
YC(0:9)^[3] FBOUTT
H
L
L
H
H
L
L
H
FBOUTC
H
L
H
L
PLL
BYPASSED/OFF
BYPASSED/OFF
On
On
Hi-Z
Hi-Z
Hi-Z
Off
Power Management
The individual output enable/disable control of the
CY2SSTV850 allows the user to implement unique power
management schemes into the design. Outputs are three-stat-
ed when disabled through the two-line interface as individual
bits are set low in Byte 0 and Byte 1 registers. The feedback
output pair (FBOUTT, FBOUTC) cannot be disabled via
two-line serial bus. The enabling and disabling of individual
outputs is done in such a manner as to eliminate the possibility
of partial “runt” clocks.
Zero-delay Buffer
When used as a zero-delay buffer the CY2SSTV850 will likely
be in a nested clock tree application. For these applications
the CY2SSTV850 offers a differential clock input pair as a PLL
reference. The CY2SSTV850 then can lock onto the reference
and translate with near zero delay to low-skew outputs. For
normal operation, the external feedback input, FBINT, is con-
nected to the feedback output, FBOUTT. By connecting the
feedback output to the feedback input the propagation delay
through the device is eliminated. The PLL works to align the
output edge with the input reference edge thus producing a
near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
When AVDD is strapped low, the PLL is turned off and by-
passed for test purposes.
Serial Control Registers
Byte0: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
1
3, 2
YT0, YC0
6
1
5, 6
YT1, YC1
5
1
10, 9
YT2, YC2
4
1
20, 19
YT3, YC3
3
1
22, 23
YT4, YC4
2
1
46, 47
YT5, YC5
1
1
44, 43
YT6, YC6
0
1
39, 40
YT7, YC7
Byte1: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
1
29, 30
YT8, YC8
6
1
27, 26
YT9, YC9
5
0
Reserved
4
0
Reserved
3
0
Reserved
2
0
Reserved
1
0
Reserved
0
0
Reserved
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
“Command Code” byte, and “Byte Count” byte.
2 Line Serial Interface
2-Line Serial Interface Slave Address
A7
A6
A5
A4
A3
A2
A1
R/W
1
1
0
1
0
0
1
0
Writing to the device is accomplished by sequentially sending the device address D2H, the dummy bytes (command code and
the number of bytes), and the data bytes. This sequence is illustrated in the following tables.
Note:
3. Each output pair can be three-stated via the two-line serial interface.
Document #: 38-07457 Rev. *A
Page 3 of 11