CY2SSTV850 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – Differential Clock Buffer/Driver

STV850
CY2SSTV850
Features
• Phase-locked loop clock distribution for Double Data
Rate Synchronous DRAM applications
• 1:10 differential outputs
• External Feedback pins (FBINT, FBINC) are used to syn-
chronize the outputs to the clock input
• SSCG: Spread Aware™ for EMI reduction
• 48-pin SSOP and TSSOP packages
• Conforms to JEDEC JC40 and JC42.5 DDR
specifications
Differential Clock Buffer/Driver
Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential
clock input pair (CLKINT, CLKINC) to ten differential pair of
clock outputs (YT[0:9], YC[0:9]) and one differential pair feed-
back clock output (FBOUTT, FBOUTC). The clock outputs are
individually controlled by the serial inputs SCLK and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL
is turned off and bypassed for test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC)
and the feedback clocks (FBINT,FBINC) to provide high-per-
formance, low-skew, low-jitter output differential clocks.
Block Diagram
Pin Configuration
SCLK
SDATA
CLKINT
CLKINC
FBINT
FBINC
AVDD
10
Serial
Interface
Logic
PLL
YT0
YC0
YT1
YC1
YT2
YC2
YT3
YC3
YT4
YC4
YT5
YC5
YT6
YC6
YT7
YC7
YT8
YC8
YT9
YC9
FBOUTT
FBOUTC
VSS
1
YC0
2
YT0
3
VDDQ
4
YT1
5
YC1
6
VSS
7
VSS
8
YC2
9
YT2
10
VDD
11
SCLK
12
CLKINT
13
CLKINC
14
VDDI
15
AVDD
16
AVSS
17
VSS
18
YC3
19
YT3
20
VDDQ
21
YT4
22
YC4
23
VSS
24
48
VSS
47
YC5
46
YT5
45
VDDQ
44
YT6
43
YC6
42
VSS
41
VSS
40
YC7
39
YT7
38
VDDQ
37
SDATA
36
FBINT
35
FBINC
34
VDDQ
33
FBOUTC
32
FBOUTT
31
VSS
30
YC8
29
YT8
28
VDDQ
27
YT9
26
YC9
25
VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07457 Rev. *A
Revised December 18, 2001