CY29946_11 Datasheet, PDF (3/9 Pages) Cypress Semiconductor – 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer 200-MHz clock support

CY29946
Absolute Maximum Conditions^[2]
Maximum Input Voltage Relative to V_SS............. V_SS – 0.3 V
Maximum Input Voltage Relative to V_DD............. V_DD + 0.3 V
Storage Temperature ................................ –65 C to +150 C
Operating Temperature............................... –40 C to +85 C
Maximum ESD protection............................................... 2 kV
Maximum Power Supply................................................ 5.5 V
Maximum Input Current ............................................. ±20 mA
DC Electrical Specifications
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V_in and V_out should be constrained to the range:
V_SS < (V_in or V_out) < V_DD .
Unused inputs must always be tied to an appropriate logic
voltage level (either V_SS or V_DD).
V_DD = V_DDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range
Parameter
Description
Conditions
Min
V_IL
V_IH
I_IL
I_IH
V_OL
V_OH
I_DDQ
I_DD
Z_Out
C_in
Input Low Voltage
V_SS
Input High Voltage
2.0
Input Low Current^[3]
–
Input High Current^[3]
–
Output Low Voltage^[4]
I_OL = 20 mA
–
Output High Voltage^[4]
I_OH = –20 mA, V_DD = 3.3 V
2.5
I_OH = –20 mA, V_DD = 2.5 V
1.8
Quiescent Supply Current
–
Dynamic Supply Current
Output Impedance
Input Capacitance
V_DD = 3.3 V, Outputs @ 100 MHz, CL = 30 pF
–
V_DD = 3.3 V, Outputs @ 160 MHz, CL = 30 pF
–
V_DD = 2.5 V, Outputs @ 100 MHz, CL = 30 pF
–
V_DD = 2.5 V, Outputs @ 160 MHz, CL = 30 pF
–
V_DD = 3.3 V
12
V_DD = 2.5 V
14
–
Typ
Max Unit
–
0.8
V
–
V_DD
V
–
–100 µA
–
100 µA
–
0.4
V
–
–
V
–
–
5
7
mA
130
–
mA
225
–
95
–
160
–
15
18
W
18
22
4
–
pF
Notes
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50  (or 50  to V_DD/2) transmission lines.
Document #: 38-07286 Rev. *G
Page 3 of 9
[+] Feedback