CY29946_11 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer 200-MHz clock support

CY29946
2.5 V or 3.3 V, 200-MHz,
1:10 Clock Distribution Buffer
2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer
Features
■ 2.5 V or 3.3 V operation
■ 200-MHz clock support
■ Two LVCMOS-/LVTTL-compatible inputs
■ Ten clock outputs: drive up to 20 clock lines
■ 1× or 1/2× configurable outputs
■ Output three-state control
■ 250-ps max output-to-output skew
■ Pin-compatible with MPC946, MPC9446
■ Available in commercial and industrial temperature range
■ 32-pin TQFP package
Block Diagram
Description
The CY29946 is a low-voltage 200-MHz clock distribution buffer
with the capability to select one of two LVCMOS/LVTTL
compatible input clocks. These clock sources can be used to
provide for test clocks as well as the primary system clocks. All
other control inputs are LVCMOS/LVTTL compatible. The
10 outputs are LVCMOS or LVTTL compatible and can drive
50  series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or two
traces giving the device an effective fanout of 1:20.
The CY29946 is capable of generating 1× and 1/2× signals from
a 1× source. These signals are generated and retimed internally
to ensure minimal skew between the 1× and 1/2× signals.
SEL(A:C) inputs allow flexibility in selecting the ratio of 1× to1/2×
outputs.
The CY29946 outputs can also be three-stated via MR/OE#
input. When MR/OE# is set HIGH, it resets the internal flip-flops
and three-states the outputs.
TCLK_SEL
TCLK0
TCLK1
DSELA
/1
0
R ^/2
1
3
QA0:2
DSELB
/1
0
R ^/2
1
3
QB0:2
DSELC
MR/OE#
/1
0
R ^/2
1
4
QC0:3
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07286 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 11, 2011
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