CY29351_09 Datasheet, PDF (3/10 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer

CY29351
Table 2. Frequency Table
Feedback Output Divider
÷2
÷4
÷8
VCO
Input Clock * 2
Input Clock * 4
Input Clock * 8
Input Frequency Range
(AVDD = 3.3V)
100 MHz to 200 MHz
50 MHz to 125 MHz
25 MHz to 62.5 MHz
Input Frequency Range
(AVDD = 2.5V)
100 MHz to 190 MHz
50 MHz to 95 MHz
25 MHz to 47.5 MHz
Table 3. Function Table
Control
REF_SEL
PLL_EN
Default
0
1
OE#
0
SELA
0
SELB
0
SELC
0
SELD
0
0
PCLK
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs enabled
÷ 2 (bank A)
÷ 4 (bank B)
÷ 4 (bank C)
÷ 4 (bank D)
1
TCLK
PLL enabled. The VCO output connects to the output
dividers
Outputs disabled (three-state), VCO running at its
minimum frequency
÷ 4 (bank A)
÷ 8 (bank B)
÷ 8 (bank C)
÷ 8 (bank D)
Absolute Maximum Conditions
Parameter
V_DD
V_DD
V_IN
V_OUT
V_TT
LU
R_PS
T_S
T_A
T_J
Ø_JC
Ø_JA
ESD_H
FIT
Description
DC supply voltage
DC operating voltage
DC input voltage
DC output voltage
Output termination voltage
Latch-up immunity
Power supply ripple
Temperature, storage
Temperature, operating ambient
Temperature, junction
Dissipation, junction to case
Dissipation, junction to ambient
ESD protection (human body model)
Failure in time
Condition
Functional
Relative to V_SS
Relative to V_SS
Functional
Ripple frequency < 100 kHz
Non Functional
Functional
Functional
Functional
Functional
Manufacturing test
Min
–0.3
2.375
–0.3
–0.3
–
200
–
–65
–40
–
2000
Max
5.5
3.465
V_DD + 0.3
V_DD + 0.3
V_DD ÷ 2
–
150
+150
+85
+150
42
105
–
10
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
Document Number: 38-07475 Rev. *C
Page 3 of 10
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