CY29351_09 Datasheet, PDF (2/10 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer

Pinout
Figure 1. Pin Diagram - 32-Pin TQFP Package
AVDD
FB_IN
SELA
SELB
SELC
SELD
AVSS
PECL_CLK
1
24 QC0
2
23 VDDQC
3
22 QC1
4
5
CY29351
21
20
VSS
QD0
6
19 VDDQD
7
18 QD1
8
17 VSS
CY29351
Table 1. Pin Definitions - 32-Pin TQFP Package
Pin^[1]
Name
I/O
Type
Description
8
PECL_CLK I, PU LVPECL LVPECL reference clock input
9
PECL_CLK# I, PU/PD LVPECL LVPECL reference clock input. Weak pull up to VDD/2.
30
TCLK
I, PD LVCMOS LVCMOS/LVTTL reference clock input
28
QA
O LVCMOS Clock output bank A
26
QB
O LVCMOS Clock output bank B
22, 24
QC(1,0)
O LVCMOS Clock output bank C
12, 14, 16, 18, 20 QD(4:0)
O LVCMOS Clock output bank D
2
FB_IN
I, PD LVCMOS Feedback clock input. Connect to an output for normal operation. This
input should be at the same voltage rail as input reference clock
10
OE#
I, PD LVCMOS Output enable/disable input
31
PLL_EN
I, PU LVCMOS PLL enable/disable input
32
REF_SEL
I, PD LVCMOS Reference select input
3, 4, 5, 6
27
23
15, 19
1
11
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
VDD
I, PD
Supply
Supply
Supply
Supply
Supply
LVCMOS Frequency select input, bank (A:D)
VDD 2.5V or 3.3V power supply for bank B output clock^[2,3]
VDD 2.5V or 3.3V power supply for bank C output clocks^[2,3]
VDD 2.5V or 3.3V power supply for bank D output clocks^[2,3]
VDD 2.5V or 3.3V power supply for PLL^[4,5]
VDD 2.5V or 3.3V power supply for core, inputs, and bank A output clock^[2,3]
7
AVSS
Supply Ground Analog ground
13, 17, 21, 25, 29 VSS
Supply Ground Common ground
Notes
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1-μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, the
high-frequency filtering characteristics are cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of V_TT. Alternatively, each output drives up to two 50 Ω series terminated
transmission lines.
5. Inputs have pull up or pull down resistors that affect the input current.
Document Number: 38-07475 Rev. *C
Page 2 of 10
[+] Feedback