CY241V8A-11 Datasheet, PDF (3/9 Pages) Cypress Semiconductor – Integrated phase locked loop (PLL)

CY241V8A-11
AC Electrical Specifications
(V_DD = 3.3 V)
Parameter ^[3]
Name
DC
Output duty cycle
ER
Rising edge rate
EF
Falling edge rate
t₉
Clock jitter
t₁₀
PLL lock time
Description
Min
Typ
Max Unit
Duty cycle is defined in Figure 3 on 45
50
55
%
page 4, 50% of V_DD
Output clock edge rate, measured 0.8
1.4
from 20%
pCa^Lg^Oe^AD4.= ¹⁵
to
pF.
80% of
See Figure
4V^Do^Dn,
–
V/ns
Output clock edge rate, measured 0.8
1.4
from 80%
pCa^Lg^Oe^AD4.= ¹⁵
to
pF.
20% of
See Figure
4V^Do^Dn,
–
V/ns
Peak-to-peak period jitter
–
–
100
ps
–
–
3
ms
Test and Measurement Setup
Figure 2. Test and Measurement Setup
VDD
0.1 F
DUT
Outputs
C_LOAD
GND
Note
3. Not 100% tested.
Document Number: 38-07654 Rev. *D
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