CY241V8A-11 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – Integrated phase locked loop (PLL)

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CY241V8A-11
MPEG Clock Generator with VCXO
MPEG Clock Generator with VCXO
Features
■ Integrated phase locked loop (PLL)
■ Low jitter, high accuracy outputs
■ VCXO with analog adjust
■ 3.3 V operation
Benefits
■ Highest performance PLL tailored for multimedia applications
■ Meets critical timing requirements in complex system designs
■ Application compatibility for a wide variety of designs
Frequency Table
Part Number
CY241V8A-11
Outputs
Input Frequency Range
Output Frequencies
VCXO Control
Curve
Other Features
1 13.5 MHz pullable crystal input One copy of 54 MHz
per Cypress specification
linear
Pinout-compatible with CY2411
Block Diagram
13.5 XIN
XOUT
OSC
PLL
Output
Divider
54 MHz
VCXO
Pin Configuration
VDD VSS
Figure 1. 8-pin SOIC pinout
Pin Descriptions
Name
XIN
VDD
VCXO
VSS
54 MHz
XOUT
Pin Number
1
Reference crystal input
2, 5
Voltage supply
3
Input analog control for VCXO
4, 7
Ground
6
54 MHz clock output
8
Reference crystal output
Description
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07654 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 21, 2012