CY14C101J_12 Datasheet, PDF (3/31 Pages) Cypress Semiconductor – 1-Mbit (128 K × 8) Serial (I2C) nvSRAM

CY14C101J
CY14B101J
CY14E101J
Pinouts
[2]
NC 1
8
A1 2 _CY14X101J1 7
A2
3
Top View
not to scale
6
V_SS 4
5
Figure 1. 8-pin SOIC pinout
V_CC
WP
SCL
SDA
V_{CAP 1}
8
A1 2 _CY14X101J2 7
A2
3
Top View
not to scale
6
V_{SS 4}
5
V_CC
WP
SCL
SDA
Figure 2. 16-pin SOIC pinout
NC 1
NC 2
NC ₃
NC ₄
WP 5
[2]
NC ₆
NC ₇
VSS ₈
16 VCC
15 NC
CY14X101J3 ¹⁴
Top View ₁₃
not to scale
12
V_CAP
A2
SDA
11 ^SCL
10 A1
9 HSB
Pin Definitions
Pin Name I/O Type
Description
SCL
SDA
Input
Clock. Runs at speeds up to a maximum of f_SCL.
Input/Output I/O. Input/Output of data through I²C interface.
Output: Is open-drain and requires an external pull-up resistor.
WP
A2–A1
Input
Input
Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be
left open if not connected.
Slave Address. Defines the slave address for I²C. This pin is internally pulled LOW and hence can be
left open if not connected.
HSB
Input/Output Hardware STORE Busy
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (t_HHHD) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
V_CAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It
must never be connected to ground.
NC
No connect No connect. This pin is not connected to the die.
V_SS Power supply Ground.
V_CC Power supply Power supply.
Note
2. This pin is reserved for lower densities.
Document Number: 001-54050 Rev. *I
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