CY14C101J_12 Datasheet, PDF (15/31 Pages) Cypress Semiconductor – 1-Mbit (128 K × 8) Serial (I2C) nvSRAM

CY14C101J
CY14B101J
CY14E101J
Current Control Registers Read
A read of Control Registers Slave is started with master sending
the Control Registers Slave address after the START condition
with the LSB set to ‘1’. The reads begin from the current address
which is the next address to the last accessed location. The
reads to Control Registers Slave continues till the last readable
address location and loops back to the first location (0x00). Note
that the Command Register is a write only register and is not
accessible through the sequential read operations. If a burst read
operation begins from the Command Register (0xAA), the
address counter wraps around to the first address in the register
map (0x00).
By Master
SDA Line
By nvSRAM
Figure 25. Control Registers Single-Byte Read
S
T
A
Control Registers
R
Slave Address
T
S
A
T
0
P
S 0 0 1 1 A2 A1 X 1
P
Data Byte
A
S
T
A
By Master
R
T
Figure 26. Current Control Registers Multi-Byte Read
Control Registers
A
Slave Address
S
AT
0
P
SDA Line
S 0 0 1 1 A2 A1 X 1
P
By nvSRAM
Data Byte
A
Data Byte N
Random Control Registers Read
A read of random address may be performed by initiating a write
operation to the intended location of read and immediately
following with a Repeated START operation. The reads to
Control Registers Slave continues till the last readable address
location and loops back to the first location (0x00). Note that the
.
Command Register is a write only register and is not accessible
through the sequential read operations. A random read starting
at the Command Register (0xAA) loops back to the first address
in the Control Registers register map (0x00). If a random read
operation is initiated from an out-of-bound memory address, the
nvSRAM sends a NACK after the address byte is sent.
S
T
A
By Master
R
T
Figure 27. Random Control Registers Single-Byte Read
Control Registers
Slave Address
Control Register Address
Control Registers Slave Address
S
T
A0
P
SDA Line
S 0 0 1 1 A2 A1 X 0
Sr 0 0 1 1 A2 A1 X 1
P
By nvSRAM
A
A
Data Byte
A
Document Number: 001-54050 Rev. *I
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