CYP15G0403DXB Datasheet, PDF (29/43 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II-TM Transceiver

PRELIMINARY
CYP15G0403DXB
CYV15G0403DXB
CYP(V)15G0403DXB AC Electrical Characteristics (continued)
Parameter
t_RXLOCK
t_RXUNLOCK
t_JTOL[18]
t_DJTOL[18]
Description
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
Receive PLL Unlock Rate
Total Jitter Tolerance^[32]
Deterministic Jitter Tolerance^[32]
IEEE 802.3z
IEEE 802.3z
Min.
600
370
Max Unit
376k UI
376k UI
46 UI
ps
ps
Capacitance ^[18]
Parameter
Description
Test Conditions
Max.
Unit
C_INTTL
C_INPECL
TTL Input Capacitance
PECL input Capacitance
T_A = 25°C, f₀ = 1 MHz, V_CC = 3.3V
T_A = 25°C, f₀ = 1 MHz, V_CC = 3.3V
7
pF
4
pF
Notes:
32. Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259, SMPTE 292, ESCON, FICON, Fibre Channel, and DVB-ASI.
Document #: 38-02065 Rev. *C
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