CYP15G0403DXB Datasheet, PDF (1/43 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II-TM Transceiver

PRELIMINARY
CYP15G0403DXB
CYV15G0403DXB
Independent Clock Quad HOTLink II™ Transceiver
Features
• Quad channel transceiver for 195- to 1500-MBaud serial
signaling rate
— Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink^® technology
• Compliant to multiple standards
— ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M,
Fibre Channel and Gigabit Ethernet (IEEE802.3z)
— 8B/10B coded data or 10 bit uncoded data
• Truly independent channels
— Each channel can operate at a different signaling
rate
— Each channel can transport a different type of data
• Selectable input/output clocking options
• Internal phase-locked loops (PLLs) with no external
PLL components
• Dual differential PECL-compatible serial inputs per
channel
— Internal DC-restoration
• Dual differential PECL-compatible serial outputs per
channel
— Source matched for 50 transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• MultiFrame™ Receive Framer provides alignment
options
— Bit and byte alignment
— Comma or Full K28.5 detect
— Single or Multi-byte Framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 3W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• 0.25 BiCMOS technology
Functional Description
The CYP(V)15G0403DXB^[1] Independent Clock Quad
HOTLink II™ Transceiver is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links like optical fiber,
balanced, and unbalanced copper transmission lines. The
signaling rate can be anywhere in the range of 195 to 1500
MBaud per serial link. Each channel operates independently
with its own reference clock allowing different rates. Each
transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and then
converts it to serial data. Each receive channel accepts serial
data and converts it to parallel data, decodes the data into
characters, and presents these characters to an Output
Register. Figure 1 illustrates typical connections between
independent host systems and corresponding
CYP(V)15G0403DXB chips.
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10
Serial Links
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10
10
10
Independent
CYP(V)15G0403DXB
Serial Links
Serial Links
Independent
CYP(V)15G0403DXB
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Serial Links
Backplane or
Cabled
Connections
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Figure 1. HOTLink II™ System Connections
Note:
1. CYV15G0403DXB refers to the SMPTE-compliant devices. CYP15G0403DXB refers to the non-SMPTE devices. CYP(V)15G0403DXB corresponds to both
SMPTE and non-SMPTE devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02065 Rev. *C
Revised June 11, 2004