CY8C36_10 Datasheet, PDF (29/112 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 3: CY8C36 Family Datasheet
Figure 6-8. GPIO Block Diagram
Digital Input Path
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Interrupt
Logic
Input Buffer Disable
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
PRT[x]DR
0
Digital System Output
1
In
PRT[x]BYP
Vddio Vddio
Vddio
PRT[x]DM2
Drive
Slew
PRT[x]DM1
Logic
Cntl
PIN
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
OE
Analog
1₀
1
0
Capsense Global Control
1
CAPS[x]CFG1
PRT[x]AG
Analog Global Enable
PRT[x]AMUX
Analog Mux Enable
Switches
LCD
PRT[x]LCD_COM_SEG
PRT[x]LCD_EN
LCD Bias Bus
5
Display
Data
Logic & MUX
Document Number: 001-53413 Rev. *I
Page 29 of 112
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