CY8C36_10 Datasheet, PDF (17/112 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 3: CY8C36 Family Datasheet
4.5 Interrupt Controller
The interrupt controller provides a mechanism for hardware
resources to change program execution to a new address,
independent of the current task being executed by the main
code. The interrupt controller provides enhanced features not
found on original 8051 interrupt controllers:
„ Thirty-two interrupt vectors
„ Jumps directly to ISR anywhere in code space with dynamic
vector addresses
„ Multiple sources for each vector
„ Flexible interrupt to vector matching
„ Each interrupt vector is independently enabled or disabled
„ Each interrupt can be dynamically assigned one of eight
priorities
„ Eight level nestable interrupts
„ Multiple I/O interrupt vectors
„ Software can send interrupts
„ Software can clear pending interrupts
When an interrupt is pending, the current instruction is
completed and the program counter is pushed onto the stack.
Code execution then jumps to the program address provided by
the vector. After the ISR is completed, a RETI instruction is
executed and returns execution to the instruction following the
previously interrupted instruction. To do this the RETI instruction
pops the program counter from the stack.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source.
Fixed function interrupts and all interrupt sources may be routed
to any interrupt vector using the UDB interrupt source
connections.
Table 4-8. Interrupt Vector Table
# Fixed Function
DMA
UDB
0 LVD
phub_termout0[0] udb_intr[0]
1 ECC
phub_termout0[1] udb_intr[1]
2 Reserved
phub_termout0[2] udb_intr[2]
3 Sleep (Pwr Mgr) phub_termout0[3] udb_intr[3]
4 PICU[0]
phub_termout0[4] udb_intr[4]
5 PICU[1]
phub_termout0[5] udb_intr[5]
6 PICU[2]
phub_termout0[6] udb_intr[6]
7 PICU[3]
phub_termout0[7] udb_intr[7]
8 PICU[4]
phub_termout0[8] udb_intr[8]
9 PICU[5]
phub_termout0[9] udb_intr[9]
10 PICU[6]
phub_termout0[10] udb_intr[10]
11 PICU[12]
phub_termout0[11] udb_intr[11]
12 PICU[15]
phub_termout0[12] udb_intr[12]
13 Comparators
Combined
phub_termout0[13] udb_intr[13]
14 Switched Caps
Combined
15 I²C
phub_termout0[14] udb_intr[14]
phub_termout0[15] udb_intr[15]
16 CAN
phub_termout1[0] udb_intr[16]
17 Timer/Counter0 phub_termout1[1] udb_intr[17]
18 Timer/Counter1 phub_termout1[2] udb_intr[18]
19 Timer/Counter2 phub_termout1[3] udb_intr[19]
20 Timer/Counter3 phub_termout1[4] udb_intr[20]
21 USB SOF Int
phub_termout1[5] udb_intr[21]
22 USB Arb Int
phub_termout1[6] udb_intr[22]
23 USB Bus Int
phub_termout1[7] udb_intr[23]
24 USB Endpoint[0] phub_termout1[8] udb_intr[24]
25 USB Endpoint Data phub_termout1[9] udb_intr[25]
26 Reserved
phub_termout1[10] udb_intr[26]
27 Reserved
phub_termout1[11] udb_intr[27]
28 DFB Int
phub_termout1[12] udb_intr[28]
29 Decimator Int
phub_termout1[13] udb_intr[29]
30 PHUB Error Int
phub_termout1[14] udb_intr[30]
31 EEPROM Fault Int phub_termout1[15] udb_intr[31]
Document Number: 001-53413 Rev. *I
Page 17 of 112
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