CY7C1546KV18 Datasheet, PDF (29/31 Pages) Cypress Semiconductor – 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1546KV18, CY7C1557KV18
CY7C1548KV18, CY7C1550KV18
Acronyms
Acronym
CMOS
DDR
DLL
FBGA
HSTL
I/O
JTAG
PLL
QDR
SEL
SRAM
TAP
TCK
TDI
TDO
TMS
Description
complementary metal oxide semiconductor
double data rate
delay lock loop
fine pitch ball gird array
high-speed transceiver logic
input/output
Joint Test Action Group
phase locked loop
quad data rate
single event latch up
static random access memory
test access port
test clock
test data in
test data out
test mode select
Document Conventions
Units of Measure
Symbol
°C
MHz
FIT/Dev
FIT/Mb
µA
µs
mm
mA
ms
ns

pF
V
W
Unit of Measure
degree Celsius
Mega Hertz
failure in time per device
failure in time per mega bit
micro Amperes
micro seconds
milli meter
milli Amperes
milli seconds
nano seconds
ohms
pico Farad
Volts
watts
Document Number: 001-15879 Rev. *I
Page 29 of 31
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