CY7C1546KV18 Datasheet, PDF (2/31 Pages) Cypress Semiconductor – 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

Logic Block Diagram (CY7C1546KV18)
CY7C1546KV18, CY7C1557KV18
CY7C1548KV18, CY7C1550KV18
A_(21:0)
22
LD
K
K
DOFF
V_REF
R/W
NWS_[1:0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
16
8
8
Logic Block Diagram (CY7C1557KV18)
Output
Logic
R/W
Control
Reg.
Reg. ⁸
Reg.
8
8
8
CQ
CQ
DQ_[7:0]
QVLD
A_(21:0)
22
LD
K
K
DOFF
V_REF
R/W
BWS_[0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
18
9
9
Output
R/W
Logic
Control
Reg.
Reg. ⁹
Reg.
9
9
9
CQ
CQ
DQ_[8:0]
QVLD
Document Number: 001-15879 Rev. *I
Page 2 of 31
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