CY14B101KA Datasheet, PDF (29/29 Pages) Cypress Semiconductor – 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock

PRELIMINARY
CY14B101KA/CY14B101MA
Document Title: CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock
Document Number: 001-42880
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*B 2654484 02/05/09
GVCH/PYRS
Changed the data sheet from Advance information to Preliminary
Changed X₁, X₂ pin names to X_out, X_in respectively
Updated Real Time Clock operation description
Added footnotes 11 and 12
Added default values to RTC Register Map” table 3
Updated flag register description in Register Map Detail” table 4
Changed C1, C2 values to 21pF, 21pF respectively
Changed I_BAK value from 350 nA to 450 nA at hot temperature
Changed V_RTCcap typical value from 2.4V to 3.0V
Referenced Note 15 to parameters t_LZCE, t_HZCE, t_LZOE, t_HZOE, t_LZBE, t_LZWE, t_HZWE-
and t_HZBE
Added footnote 24
Updated Figure 13
*C 2733909 07/09/09
GVCH/AESA
Page 3; Added note to AutoStore Operation description
Page 4; Updated Hardware STORE (HSB) Operation description
Page 4; Updated Software STORE Operation description
Added best practices
Changed C1, C2 values to 10pF, 67pF respectively
Changed I_BAK and V_RTCcap parameter values
Added R_BKCHG parameter
Updated V_HDIS parameter description
Updated t_DELAY parameter description
Updated footnote 28 and added footnote 35
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Document #: 001-42880 Rev. *C
Revised July 09, 2009
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