CY14B101KA Datasheet, PDF (17/29 Pages) Cypress Semiconductor – 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock

PRELIMINARY
CY14B101KA/CY14B101MA
AC Switching Characteristics
Parameters
Cypress
Parameters
Alt
Parameters
SRAM Read Cycle
t_ACE
t_ACS
t_RC ^[19]
t_RC
t_AA ^[20]
t_AA
t_DOE
t_OE
t_OHA[20]
t_OH
t_LZCE ^{[16, 21]}
t_LZ
t_HZCE ^{[16, 21]}
t_HZ
t_LZOE ^{[16, 21]}
t_OLZ
t_HZOE ^{[16, 21]}
t_OHZ
t_PU ^[16]
t_PA
t_PD ^[16]
t_PS
t_DBE
-
t_LZBE[16]
-
t_HZBE[16]
-
SRAM Write Cycle
t_WC
t_WC
t_PWE
t_WP
t_SCE
t_CW
t_SD
t_DW
t_HD
t_DH
t_AW
t_AW
t_SA
t_AS
t_HA
t_WR
t_HZWE ^{[16, 21, 22] t}WZ
t_LZWE ^{[16, 21]}
t_OW
t_BW
-
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Byte Enable to Data Valid
Byte Enable to Output Active
Byte Disable to Output Inactive
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
Byte Enable to End of Write
20 ns
Min Max
25 ns
Min Max
20
25
20
25
20
25
10
12
3
3
3
3
8
10
0
0
8
10
0
0
20
25
10
12
0
0
8
10
20
25
15
20
15
20
8
10
0
0
15
20
0
0
0
0
8
10
3
3
15
20
Switching Waveforms
Figure 7. SRAM Read Cycle #1: Address Controlled ^{[19, 20, 23]}
t_RC
Address
Address Valid
t_AA
45 ns
Min Max
45
45
45
20
3
3
15
0
15
0
45
20
0
15
45
30
30
15
0
30
0
0
15
3
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Output
Previous Data Valid
t_OHA
Output Data Valid
Notes
19. WE must be HIGH during SRAM read cycles.
20. Device is continuously selected with CE, OE and BHE/BLE LOW.
21. Measured ±200 mV from steady state output voltage.
22. If WE is low when CE goes low, the outputs remain in the high impedance state.
23. HSB must remain HIGH during Read and Write cycles.
Document #: 001-42880 Rev. *C
Page 17 of 29
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