CY8C36_12 Datasheet, PDF (27/131 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C36 Family
Data Sheet
3-62 MHz
IMO
4-25 MHz
ECO
Figure 6-1. Clocking Subsystem
External IO
or DSI
0-66 MHz
32 kHz ECO
1,33,100 kHz
ILO
48 MHz
Doubler for
USB
24-67 MHz
PLL
Master
Mux
CPU Clock Divider
4 bit
CPU
Clock
Bus Clock Divider
16 bit
Bus
Clock
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
s
Analog Clock k
Divider 16 bit e
w
s
Analog Clock k
Divider 16 bit e
w
7
s
Analog Clock k
Divider 16 bit e
w
s
Analog Clock k
Divider 16 bit e
w
Table 6-1. Oscillator Summary
Source
IMO
MHzECO
Fmin
3 MHz
4 MHz
Tolerance at Fmin
±1% over voltage and temperature
Crystal dependent
DSI
PLL
Doubler
ILO
0 MHz
24 MHz
48 MHz
1 kHz
Input dependent
Input dependent
Input dependent
–50%, +100%
kHzECO
32 kHz Crystal dependent
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±7% at 62 MHz. The
IMO, in conjunction with the PLL, allows generation of other
clocks up to the device's maximum frequency (see
Phase-Locked Loop).
The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz.
Fmax
62 MHz
25 MHz
Tolerance at Fmax
±7%
Crystal dependent
66 MHz
67 MHz
48 MHz
100 kHz
Input dependent
Input dependent
Input dependent
–55%, +100%
32 kHz Crystal dependent
Startup Time
13 µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler worksat input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
Document Number: 001-53413 Rev. *O
Page 27 of 131