CY8C36_12 Datasheet, PDF (25/131 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C36 Family
Data Sheet
5.7.5 I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in I/O System and Routing on page 34.
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
Each SFR supported I/O port provides three SFRs:
 SFRPRTxDR sets the output data state of the port (where × is
port number and includes ports 0–6, 12 and 15).
 The SFRPRTxSEL selects whether the PHUB PRTxDR
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
 The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
5.7.5.1 xdata Space
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not “external”—it is used by on-chip components.
See Table 5-5. External, that is, off-chip, memory can be
accessed using the EMIF. See External Memory Interface on
page 23.
Table 5-5. XDATA Data Address Map
Address Range
0×00 0000 – 0×00 1FFF
0×00 4000 – 0×00 42FF
0×00 4300 – 0×00 43FF
0×00 4400 – 0×00 44FF
0×00 4500 – 0×00 45FF
0×00 4700 – 0×00 47FF
0×00 4800 - 0×00 48FF
0×00 4900 – 0×00 49FF
0×00 4E00 – 0×00 4EFF
0×00 4F00 – 0×00 4FFF
0×00 5000 – 0×00 51FF
0×00 5400 – 0×00 54FF
0×00 5800 – 0×00 5FFF
0×00 6000 – 0×00 60FF
0×00 6400 – 0×00 6FFF
0×00 7000 – 0×00 7FFF
0×00 8000 – 0×00 8FFF
0×00 A000 – 0×00 A400
0×00 C000 – 0×00 C800
0×01 0000 – 0×01 FFFF
0×05 0220 – 0×05 02F0
0×08 0000 – 0×08 1FFF
0×80 0000 – 0×FF FFFF
Purpose
SRAM
Clocking, PLLs, and oscillators
Power management
Interrupt controller
Ports interrupt control
Flash programming interface
Cache controller
I²C controller
Decimator
Fixed timer/counter/PWMs
I/O ports control
External Memory Interface
(EMIF) control registers
Analog Subsystem interface
USB controller
UDB configuration
PHUB configuration
EEPROM
CAN
Digital Filter Block
Digital Interconnect
configuration
Debug controller
flash ECC bytes
External Memory Interface
Document Number: 001-53413 Rev. *O
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