CY8C27143_09 Datasheet, PDF (27/53 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Figure 11. Basic Switch Mode Pump Circuit
D1
+
V_BAT
L₁
Battery
Vdd
V _PUMP
C1
SMP
PSoC ^TM
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 24. Silicon Revision A – 5V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2^[6]
AGND = 2 x BandGap^[6]
AGND = P2[4] (P2[4] = Vdd/2)^[6]
AGND = BandGap^[6]
AGND = 1.6 x BandGap^[6]
AGND Block to Block Variation
(AGND = Vdd/2)^[6]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6]
(P2[6] = 1.3V)
RefHi = P2[4] + BandGap
(P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6]
(P2[6] = 1.3V)
RefLo = P2[4] – BandGap
(P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
Min
1.274
Vdd/2 - 0.030
2 x BG - 0.043
P2[4] - 0.013
BG - 0.009
1.6 x BG - 0.018
-0.034
Vdd/2 + BG - 0.140
3 x BG - 0.112
2 x BG + P2[6] - 0.113
P2[4] + BG - 0.130
P2[4] + P2[6] - 0.133
3.2 x BG - 0.112
Vdd/2 - BG - 0.051
BG - 0.082
2 x BG - P2[6] - 0.084
P2[4] - BG - 0.056
P2[4] - P2[6] - 0.057
Typ
1.30
Vdd/2 - 0.004
2 x BG - 0.010
P2[4]
BG
1.6 x BG
0.000
Vdd/2 + BG - 0.018
3 x BG - 0.018
2 x BG + P2[6] - 0.018
P2[4] + BG - 0.016
P2[4] + P2[6] - 0.016
3.2 x BG
Vdd/2 - BG + 0.024
BG + 0.023
2 x BG - P2[6] + 0.025
P2[4] - BG + 0.026
P2[4] - P2[6] + 0.026
Max
Unit
1.326
V
Vdd/2 + 0.003
V
2 x BG + 0.024
V
P2[4] + 0.014
V
BG + 0.009
V
1.6 x BG + 0.018
V
0.034
V
Vdd/2 + BG + 0.103 V
3 x BG + 0.076
V
2 x BG + P2[6] + 0.077 V
P2[4] + BG + 0.098
V
P2[4] + P2[6] + 0.100 V
3.2 x BG + 0.076
V
Vdd/2 - BG + 0.098
V
BG + 0.129
V
2 x BG - P2[6] + 0.134 V
P2[4] - BG + 0.107
V
P2[4] - P2[6] + 0.110 V
Note
6. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Document Number: 38-12012 Rev. *M
Page 27 of 53
[+] Feedback