CY8C27143_09 Datasheet, PDF (13/53 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Table 8. 48-Pin Part Pinout (QFN)*
34 IO
I P2[0] Direct switched capacitor block input.
35 IO
I P2[2] Direct switched capacitor block input.
36 IO
P2[4] External Analog Ground (AGND).
37 IO
P2[6] External Voltage Reference (VRef).
38 IO
I P0[0] Analog column mux input.
39 IO
IO P0[2] Analog column mux input and column
output.
40 IO
IO P0[4] Analog column mux input and column
output.
41 IO
I P0[6] Analog column mux input.
42
Power
Vdd Supply voltage.
43 IO
I P0[7] Analog column mux input.
44 IO
IO P0[5] Analog column mux input and column
output.
45 IO
IO P0[3] Analog column mux input and column
output.
46 IO
I P0[1] Analog column mux input.
47 IO
P2[7]
48 IO
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* The QFN package has a center pad that must be connected to ground (Vss).
** These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
Page 13 of 53
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