CY7C1511KV18_09 Datasheet, PDF (27/31 Pages) Cypress Semiconductor – 72-Mbit QDR II SRAM 4-Word Burst Architecture

CY7C1511KV18, CY7C1526KV18
CY7C1513KV18, CY7C1515KV18
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence^{[28, 29, 30]}
NOP
READ
WRITE
READ
WRITE NOP
1
2
3
4
5
6
7
K
t _KH
tKL
t _CYC
t _KHKH
K
RPS
WPS
A
D
t _SC tHC
t _SC t _HC
A0
tSA tHA
A1
A2
A3
tHD
t _HD
tSD
tSD
D10 D11 D12 D13 D30 D31 D32 D33
Q
t _KHCH
C
C
CQ
t _CQH
CQ
t _KHCH
t _CLZ
Q00
Q01 Q02
tCO
Q03 Q20
tCQDOH
Q21
Q22 Q23
t _CHZ
tDOH
tCQD
t _CYC
t _KHKH
t _{KH tKL}
t _CQHCQH
t _CQOH
t _CCQO
t _CQOH
t _CCQO
DON’T CARE
UNDEFINED
Notes
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
29. Outputs are disabled (High-Z) one clock cycle after a NOP.
30. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
Document Number: 001-00435 Rev. *G
Page 27 of 31
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