CY7C1471BV33 Datasheet, PDF (27/32 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Switching Waveforms (continued)
Figure 7 shows ZZ Mode timing waveform.^{[24, 25]}
Figure 7. ZZ Mode Timing
CLK
ZZ
I _SUPPLY
ALL INPUTS
(except ZZ)
Outputs (Q)
t _ZZ
t _ZZI
I _DDZZ
t _ZZREC
High-Z
DON’T CARE
t _RZZI
DESELECT or READ Only
Notes
24. Device must be deselected when entering ZZ mode. See the The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.^{[1, 2, 3, 4, 5, 6, 7]}
on page 11 for all possible signal conditions to deselect the device.
Document #: 001-15029 Rev. *B
Page 27 of 32
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