CY7C1471BV33 Datasheet, PDF (22/32 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on V_DD Relative to GND ........–0.5V to +4.6V
Supply Voltage on V_DDQ Relative to GND ...... –0.5V to +V_DD
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to V_DDQ + 0.5V
Electrical Characteristics
Over the Operating Range^{[13, 14]}
DC Input Voltage ................................... –0.5V to V_DD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V_DD
3.3V –5%/+10%
V_DDQ
2.5V – 5%
to V_DD
Parameter
Description
V_DD
V_DDQ
Power Supply Voltage
IO Supply Voltage
V_OH
Output HIGH Voltage
V_OL
Output LOW Voltage
V_IH
Input HIGH Voltage^[13]
V_IL
Input LOW Voltage^[13]
I_X
Input Leakage Current
except ZZ and MODE
Input Current of MODE
Input Current of ZZ
I_OZ
I_DD ^[15]
I_SB1
I_SB2
I_SB3
I_SB4
Output Leakage Current
V_DD Operating Supply
Current
Automatic CE
Power Down
Current—TTL Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—TTL Inputs
Test Conditions
For 3.3V IO
For 2.5V IO
For 3.3V IO, I_OH = –4.0 mA
For 2.5V IO, I_OH = –1.0 mA
For 3.3V IO, I_OL = 8.0 mA
For 2.5V IO, I_OL = 1.0 mA
For 3.3V IO
For 2.5V IO
For 3.3V IO
For 2.5V IO
GND ≤ V_I ≤ V_DDQ
Min
3.135
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
Max Unit
3.6
V
V_DD
V
2.625 V
V
V
0.4
V
0.4
V
V_DD + 0.3V V
V_DD + 0.3V V
0.8
V
0.7
V
5
μA
Input = V_SS
–30
Input = V_DD
Input = V_SS
–5
Input = V_DD
GND ≤ V_I ≤ V_DD, Output Disabled
–5
V_DD = Max., I_OUT = 0 mA,
f = f_MAX = 1/t_CYC
7.5 ns cycle, 133 MHz
10 ns cycle, 117 MHz
V_DD = Max, Device Deselected,
V_IN ≥ V_IH or V_IN ≤ V_IL
f = f_MAX, inputs switching
V_DD = Max, Device Deselected,
V_IN ≤ 0.3V or V_IN > V_DD – 0.3V,
f = 0, inputs static
7.5 ns cycle, 133 MHz
10 ns cycle, 117 MHz
All speeds
V_DD = Max, Device Deselected, or 7.5 ns cycle, 133 MHz
V_IN ≤ 0.3V or V_IN > V_DDQ – 0.3V _{10 ns cycle, 117 MHz}
f = f_MAX, inputs switching
V_DD = Max, Device Deselected, All Speeds
V_IN ≥ V_DD – 0.3V or V_IN ≤ _0.3V,
f = 0, inputs static
μA
5
μA
μA
30
μA
5
μA
305 mA
275 mA
200 mA
200 mA
120 mA
200 mA
200 mA
165 mA
Notes
13. Overshoot: V_IH(AC) < V_DD +1.5V (pulse width less than t_CYC/2). Undershoot: V_IL(AC) > –2V (pulse width less than t_CYC/2).
14. T_Power-up: assumes a linear ramp from 0V to V_DD(min.) within 200 ms. During this time V_IH < V_DD and V_DDQ < V_DD.
15. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-15029 Rev. *B
Page 22 of 32
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