CYRF6936 Datasheet, PDF (26/40 Pages) Cypress Semiconductor – WirelessUSB™ LP 2.4 GHz Radio SoC

CYRF6936
Mnemonic
TX_OVERRIDE_ADR
Address
0x1F
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
ACK TX
FRC PRE
RSVD MAN TXACK OVRD ACK DIS TXCRC
RSVD
TX INV
This register provides the ability to override some automatic features of the device.
Bit 7
When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the
given channel when automatically entering transmit mode.
Bit 6
Bit 5
Bit 4
Force Preamble. When this bit is set, the device transmits a continuous repetition of the preamble pattern (see
PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures. Firmware should set bit
RST of MODE_OVERRIDE_ADR to exit this mode.
Reserved. Must be zero.
Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set.
Bit 3
Bit 2
ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet.
Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets.
Bit 1
Bit 0
Reserved. Must be zero.
TX Data Invert. When this bit is set the transmit bitstream is inverted.
Mnemonic
XTAL_CFG_ADR
Address
0x26
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Function
RSVD
RSVD
RSVD
RSVD
START DLY
RSVD
RSVD
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:4
Reserved. Must be zero.
Bit 3
Crystal Startup Delay. Setting this bit, sets the crystal startup delay to 150 μs to handle warm restarts of the crystal. Firmware
MUST set this bit during initialization.
Bits 2:0
Reserved. Must be zero.
Mnemonic
CLK_OVERRIDE_ADR
Address
Bit
7
6
5
4
3
2
1
Default
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
Function
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
This register provides the ability to override some automatic features of the device.
Bits 7:2
Reserved. Must be zero.
Bit 1
Force Receive Clock. Streaming applications MUST set this bit during receive mode, otherwise this bit is cleared.
Bit 0
Reserved. Must be zero.
0x27
0
0
W
RSVD
Document #: 38-16015 Rev. *G
Page 26 of 40
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