CY7C1566KV18_11 Datasheet, PDF (26/31 Pages) Cypress Semiconductor – 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
Switching Waveforms
Read/Write/Deselect Sequence ^{[35, 36, 37]}
Figure 5. Waveform for 2.5 Cycle Read Latency
NOP
1
READ
2
READ
3
NOP
4
NOP NOP
5
6
WRITE WRITE READ NOP NOP
7
8
9
10
11
12
K
tKH tKL
tCYC tKHKH
K
LD
R/W
A
QVLD
DQ
CQ
CQ
tSC tHC
A0
tSA tHA
A1
t_QVLD
t _QVLD
A2
A3
A4
t_QVLD
tHD
tHD
tSD
tSD
Q00 Q01 Q10 Q11
D20 D21 D30 D31
Q40
tCLZ
tCO
(Read Latency = 2.5 Cycles)
tCCQO
tCQOH
tDOH
tCHZ
tCQD
t _CQDOH
tCQOH
tCCQO
tCQH
tCQHCQH
DON’T CARE
UNDEFINED
Notes
35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
36. Outputs are disabled (High Z) one clock cycle after a NOP.
37. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-15880 Rev. *K
Page 26 of 31
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