CY7C1566KV18_11 Datasheet, PDF (22/31 Pages) Cypress Semiconductor – 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with Power Applied –55 °C to +125 °C
Supply Voltage on V_DD Relative to GND ......–0.5 V to +2.9 V
Supply Voltage on V_DDQ Relative to GND ..... –0.5 V to +V_DD
DC Applied to Outputs in High Z .......–0.5 V to V_DDQ + 0.3 V
DC Input Voltage ^[18]............................ –0.5 V to V_DD + 0.3 V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015). > 2,001 V
Latch up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature (T_A)
0 °C to +70 °C
–40 °C to +85 °C
V_DD ^[19]
1.8 ± 0.1 V
V_DDQ ^[19]
1.4 V to
V_DD
Neutron Soft Error Immunity
Parameter Description
Test
Conditions
Typ
Max*
Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
197 216 FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25 °C
0 0.01 FIT/
Mb
SEL
Single Event
85 °C
0
0.1 FIT/
Latch up
Dev
* No LMBU or SEL events occurred during testing; this column
represents a statistical ², 95% confidence limit calculation. For
more details refer to Application Note AN54908 “Accelerated
Neutron SER Testing and Calculation of Terrestrial Failure Rates”
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range ^[20]
Parameter
Description
Test Conditions
V_DD
V_DDQ
V_OH
V_OL
V_OH(LOW)
V_OL(LOW)
V_IH
V_IL
I_X
I_OZ
V_REF
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Note 21
Output LOW Voltage
Note 22
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
I_OH =0.1 mA, Nominal Impedance
I_OL = 0.1 mA, Nominal Impedance
Input LOW Voltage
Input Leakage Current
GND  V_I  V_DDQ
Output Leakage Current GND  V_I  V_DDQ, Output Disabled
Input Reference Voltage ^[23] Typical Value = 0.75 V
Min
1.7
1.4
V_DDQ/2 – 0.12
V_DDQ/2 – 0.12
V_DDQ – 0.2
V_SS
V_REF + 0.1
–0.15
2
2
0.68
Typ
1.8
1.5
–
–
–
–
–
–
–
–
0.75
Max
1.9
V_DD
V_DDQ/2 + 0.12
V_DDQ/2 + 0.12
V_DDQ
0.2
V_DDQ + 0.15
V_REF – 0.1
2
2
0.95
Unit
V
V
V
V
V
V
V
V
A
A
V
Notes
18. Overshoot: V_IH(AC) < V_DDQ + 0.3 V (Pulse width less than t_CYC/2), Undershoot: V_IL(AC) > 0.3 V (Pulse width less than t_CYC/2).
19. Power up: assumes a linear ramp from 0 V to V_DD(min) within 200 ms. During this time V_IH < V_DD and V_DDQ < V_DD.
20. All Voltage referenced to Ground.
21. Outputs are impedance controlled. I_OH = –(V_DDQ/2)/(RQ/5) for values of 175  < RQ < 350 .
22. Outputs are impedance controlled. I_OL = (V_DDQ/2)/(RQ/5) for values of 175  < RQ < 350 .
23. V_REF(min) = 0.68 V or 0.46 V_DDQ, whichever is larger, V_REF(max) = 0.95 V or 0.54 V_DDQ, whichever is smaller.
Document Number: 001-15880 Rev. *K
Page 22 of 31
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