CY7C603XX_11 Datasheet, PDF (25/39 Pages) Cypress Semiconductor – enCoRe™ III Low Voltage

CY7C603xx
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < T_A < 70 °C, or 2.4 V to 3.0 V and 0 °C < T_A < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 24. 3.3 V AC Digital Block Specifications
Function
All Functions
Timer/
Counter/
PWM
Dead Band
SPIM
Description
Block input clock frequency
Enable input pulse width
Input clock frequency
Kill pulse width:
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
Input clock frequency
Min Typ
–
–
50^[17]
–
–
–
Max
24.6
–
24.6
20
–
–
50
–
–
50
–
–
–
–
24.6
–
–
8.2
SPIS
Input clock frequency
–
–
4.1
Width of SS_ Negated between transmissions 50
Transmitter Input clock frequency
–
–
–
–
24.6
Receiver
Input clock frequency
–
–
24.6
Unit
MHz
ns
MHz
Notes
3.0 V < Vdd < 3.6 V.
ns
ns
ns
MHz
MHz
MHz
ns
MHz
MHz
3.0 V  Vdd  3.6 V.
The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
Note for SPIS Input Clock
Frequency: The input clock is the
SPI SCLK in SPIS mode.
The baud rate is equal to the input
clock frequency divided by 8.
The baud rate is equal to the input
clock frequency divided by 8.
Table 25. 2.7 V AC Digital Block Specifications
Function
Description
All
Block input clock frequency
Functions
Timer/
Counter/
PWM
Enable input clock width
Input clock frequency
Dead Band Kill pulse width:
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
SPIM
Input clock frequency
Min Typ Max
–
–
12.7
100
–
–
–
–
12.7
20
–
–
100
–
–
100
–
–
–
–
12.7
–
–
6.35
SPIS
Input clock frequency
–
–
4.1
Width of SS_ Negated between transmissions 100
–
–
Transmitter Input clock frequency
–
–
12.7
Receiver Input clock frequency
–
–
12.7
Unit
Notes
MHz 2.4 V  Vdd  3.0 V.
ns
MHz
ns
ns
ns
MHz
MHz
MHz
ns
MHz
MHz
2.4 V  Vdd 3.0 V.
The SPI serial clock (SCLK) frequency
is equal to the input clock frequency
divided by 2.
Note for input clock frequency:
The input clock is the SPI SCLK in
SPIS mode.
The baud rate is equal to the input
clock frequency divided by 8.
The baud rate is equal to the input
clock frequency divided by 8.
Note
17. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-16018 Rev. *L
Page 25 of 39
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