CY7C25632KV18_13 Datasheet, PDF (25/31 Pages) Cypress Semiconductor – 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C25632KV18
CY7C25652KV18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency ^{[40, 41, 42]}
NOP
READ WRITE READ WRITE NOP
1
2
3
4
5
6
7
8
K
tKH tKL
K
tCYC
tKHKH
RPS
WPS
A
D
QVLD
Q
CQ
CQ
tSC tHC
t _SC tHC
A0
A1
A2
A3
tSA tHA
t _HD
t _SD
D10
tSD
D11 D12
t _QVLD
tCLZ ^tCO
t _HD
D13 D30 D31
tDOH
tCQD
D32 D33
tQVLD
tCQDOH
tCHZ
(Read Latency = 2.5 Cycles)
Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23
tCQOH
tCCQO
tCQH ^tCQHCQH
tCQOH
tCCQO
DON’T CARE
UNDEFINED
Notes
40. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
41. Outputs are disabled (High Z) one clock cycle after a NOP.
42. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
Document Number: 001-66482 Rev. *D
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