CY14B104K_1106 Datasheet, PDF (25/35 Pages) Cypress Semiconductor – 4-Mbit (512 K x 8/256 K x 16) nvSRAM with Real Time Clock 25 ns and 45 ns access times

CY14B104K, CY14B104M
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
Table 5. Truth Table for × 8 Configuration
CE
WE
OE
Inputs and Outputs^[52]
H
X
X High Z
L
H
L Data out (DQ₀–DQ₇)
L
H
H High Z
L
L
X Data in (DQ₀–DQ₇)
Mode
Deselect/Power-down
Read
Output disabled
Write
Table 6. Truth Table for × 16 Configuration
CE
WE
OE BHE^[53] BLE^[53] Inputs and Outputs^[52]
H
X
X
X
X High Z
L
X
X
H
H High Z
L
H
L
L
L Data out (DQ₀–DQ₁₅)
L
H
L
H
L Data out (DQ₀–DQ₇);
DQ₈–DQ₁₅ in High Z
L
H
L
L
H Data out (DQ₈–DQ₁₅);
DQ₀–DQ₇ in High Z
L
H
H
L
L High Z
L
H
H
H
L High Z
L
H
H
L
H High Z
L
L
X
L
L Data in (DQ₀–DQ₁₅)
L
L
X
H
L Data in (DQ₀–DQ₇);
DQ₈–DQ₁₅ in High Z
L
L
X
L
H Data in (DQ₈–DQ₁₅);
DQ₀–DQ₇ in High Z
Mode
Deselect/Power-down
Output disabled
Read
Read
Read
Output disabled
Output disabled
Output disabled
Write
Write
Write
Power
Standby
Active
Active
Active
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Notes
52. Data DQ₀–DQ₇ for × 8 configuration and Data DQ₀–DQ₁₅ for × 16 configuration.
53. BHE and BLE are applicable for × 16 configuration only.
Document #: 001-07103 Rev. *U
Page 25 of 35
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