CY14B104K_1106 Datasheet, PDF (1/35 Pages) Cypress Semiconductor – 4-Mbit (512 K x 8/256 K x 16) nvSRAM with Real Time Clock 25 ns and 45 ns access times

CY14B104K, CY14B104M
4-Mbit (512 K × 8/256 K × 16) nvSRAM
with Real Time Clock
4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Features
■ Watchdog timer
■ 25 ns and 45 ns access times
■ Internally organized as 512 K × 8 (CY14B104K) or 256 K × 16
(CY14B104M)
■ Clock alarm with programmable interrupts
■ Capacitor or battery backup for RTC
■ Industrial temperature
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements is initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM is initiated by software or power-up
■ High reliability
■ Infinite read, write, and RECALL cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20%, –10% operation
■ Data integrity of Cypress nvSRAM combined with full-featured
real time clock (RTC)
■ 44-pin and 54-pin thin small outline package (TSOP) Type II
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104K and CY14B104M combines a 4-Mbit
non-volatile static RAM (nvSRAM) with a full-featured RTC in a
monolithic integrated circuit. The embedded non-volatile
elements incorporate QuantumTrap technology producing the
world’s most reliable non-volatile memory. The SRAM is read
and written infinite number of times, while independent
non-volatile data resides in the non-volatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
Logic Block Diagram ^{[1, 2, 3]}
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₁₇
A₁₈
Quatrum
Trap
V_CC
V_CA
P
2048 X 2048
R
O
STORE
POWER
CONTROL
V_RTCbat
V_RTCcap
W
RECALL
D
E
STATIC RAM
C
ARRAY
O
2048 X 2048
D
E
R
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A₁₄ - A₂
DQ₀
DQ₁
DQ₂
DQ₃
DQ₄
DQ₅
DQ₆
DQ₇
DQ₈
DQ₉
DQ₁₀
DQ₁₁
DQ₁₂
DQ₁₃
DQ₁₄
DQ₁₅
I
N
P
U
T
B
COLUMN I/O
U
F
F
E
R
COLUMN DEC
S
A₉ A₁₀ A₁₁ A₁₂ A₁₃ A₁₄ A₁₅ A₁₆
RTC
MUX
X_out
X_in
INT
A₁₈- A₀
OE
WE
CE
BLE
BHE
Notes
1. Address A₀–A₁₈ for × 8 configuration and Address A₀–A₁₇ for × 16 configuration.
2. Data DQ₀–DQ₇ for × 8 configuration and Data DQ₀–DQ₁₅ for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-07103 Rev. *U
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 12, 2011
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